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tb6560ahq/afg 2011-01-18 1 toshiba bicd integrated ci rcuit silicon monolithic tb6560ahq, TB6560AFG pwm chopper-type bipolar driver ic for stepping motor control the tb6560ahq/afg is a pwm chopper-type stepping motor driver ic designed for sinusoidal-input microstep control of bipolar stepping motors. the tb6560ahq/afg can be used in applications that require 2-phase, 1-2-phase, 2w1-2-phase and 4w1-2-phase excitation modes. the tb6560ahq/afg is capable of low-vibration, high-performance forward and reverse driving of a two-phase bipolar stepping motor using only a clock signal. features ? single-chip motor driver for sinusoidal microstep control of stepping motors ? high output withstand voltage du e to the use of bicd process: ron (upper and lower sum) = tb6560ahq: 0.6 (typ.) TB6560AFG: 0.7 (typ.) ? forward and reverse rotation ? selectable phase excitation modes (2, 1-2, 2w1-2 and 4w1-2) ? high output withstand voltage: v dss = 40 v ? high output current: i out = tb6560ahq: 3.5 a (peak) TB6560AFG: 2.5 a (peak) ? packages: hzip25-p-1.27 hqfp64-p-1010-0.50 ? internal pull-down resistors on inputs: 100 k (typ.) ? output monitor pin: m o current (i mo (max) = 1 ma) ? reset and enable pins ? thermal shutdown (tsd) * : these ics are highly sensitive to electrostatic disc harge. when handling them, ensur e that the environment is protected against electrostatic discharge. ensure also that the ambient temperatur e and relative humidity are maintained at reasonable level. tb6560ahq TB6560AFG weight hzip25-p-1.27: 9.86 g (typ.) hqfp64-p-1010-0.50: 0.26 g (typ.) *solderability 1. use of sn-37pb solder bath *solder bath temperature = 230c *dipping time = 5 seconds *number of times = once *use of r-type flux 2. use of sn-3.0ag-0.5cu solder bath *solder bath temperature = 245c *dipping time = 5 seconds *the number of times = once *use of r-type flux
tb6560ahq/afg 2011-01-18 2 block diagram m1 m2 cw/ccw clk reset enable dcy1 dcy2 osc input circuit osc v dd maximum current setting circuit thermal shutdown circuit protect m o bridge driver a vm a out_ap n fa vm b bridge driver b out_bp out_bm n fb tq1 tq2 sgnd pgnda 10/64 1/42 2/43 11/2, 4 9/61, 62 12/6, 7 8/55, 56 14/13, 14 13/10, 11 16/19, 20 18/25, 26 17/23 19/28 20/30, 31 23/36 22/35 21/33 3/45 5/48 4/47 25/39 24/38 7/53 15/16 6/50, 51 tb6560ahq/TB6560AFG pwm control circuit pwm control circuit out_am pgndb
tb6560ahq/afg 2011-01-18 3 pin functions pin no. tb6560 ahq tb6560 afg i/o symbol functional description remarks 1 42 input tq2 torque setting input (current setting) internal pull-down resistor 2 43 input tq1 torque setting input (current setting) internal pull-down resistor 3 45 input clk clock input for microstepping internal pull-down resistor 4 47 input enable h: enable; l: all outputs off internal pull-down resistor 5 48 input reset l: reset (the outputs are reset to their initial states.) internal pull-down resistor 6 50/51 ? sgnd signal ground (for control block) (note 1) 7 53 ? osc a cr oscillation circuit is connec ted to this pin. performs output chopping. 8 55/56 input vm b motor power supply pin (for phase-b driver) (note 1) 9 61/62 output out_bm out_b output (note 1) 10 64 (*) ? pgndb power ground 11 2/4 (*) ? n fb connection pin for a b-channel current sensing resistor two pins of the TB6560AFG should be short-circuited. (note 1) 12 6/7 output out_bp out_b output (note 1) 13 10/11 output out_am out_a output (note 1) 14 13/14 (*) ? n fa connection pin for an a-channel current sensing resistor two pins of the TB6560AFG should be short-circuited. (note 1) 15 16 ? pgnda power ground 16 19/20 output out_ap out_a output (note 1) 17 23 output m o initial state sensing output. this pin is enabled in the initial state. open drain 18 25/26 input vm a motor power supply pin (for phase-a driver) (note 1) 19 28 output protect when tsd is activated: high; when in normal state: high-z. open drain 20 30/31 input v dd power supply pin for control block (note 1) 21 33 input cw/ccw rotation direction select input. l: clockwise; h: counterclockwise internal pull-down resistor 22 35 input m2 excitation mode setting input internal pull-down resistor 23 36 input m1 excitation mode setting input internal pull-down resistor 24 38 input dcy2 current decay mode setting input internal pull-down resistor 25 39 input dcy1 current decay mode setting input internal pull-down resistor (*): the pin assignment of the TB6560AFG is different from that of the tb6560fg. tb6560ahq: there is no no-connect (nc) pin. TB6560AFG: except the above pins, all pins are nc. the pin nu mbers of nc pins are: 1, 3, 5, 8, 9, 12, 15, 17, 18, 21, 22, 24, 27, 29, 32, 34, 37, 40, 41, 44, 46, 49, 52, 54, 57, 58, 59, 60, and 63. applying a voltage to nc pins does not cause any prob lem since they are not connected inside the ic. all control input pins have an internal pull-down resistor of 100 k (typ.) note 1: as for the TB6560AFG, two pins that have the same functionality should be short-circuited at a location as close to the TB6560AFG as possible. (the electrical characteristics provided in this documen t are measured when those pins are handled in this manner.)
tb6560ahq/afg 2011-01-18 4 equivalent circuits input pins (m1, m2, clk, cw/ccw, tq1,tq2,enable, reset ,dcy1, dcy2) output pins (m o , protect) v dd 100 k 100 100
tb6560ahq/afg 2011-01-18 5 pin assignment (top view) TB6560AFG tb6560ahq (nc) 49 sgnd 50 sgnd 51 (nc) 52 osc 53 (nc) 54 vm b 55 vm b 56 (nc) 57 (nc) 58 (nc) 59 (nc) 60 out_bm 61 out_bm 62 (nc) 63 pgndb 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 (nc) 31 v dd 30 v dd 29 (nc) 28 protect 27 (nc) 26 vm a 25 vm a 24 (nc) 23 m o 22 (nc) 21 (nc) 20 out_ap 19 out_ap 18 (nc) 17 (nc) (nc) out_bp out_bp n fb (nc) n fb (nc) (nc) (nc) out_am out_am (nc) n f a n f a (nc) pgnd a 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 reset (nc) enable clk (nc) tq1 tq2 (nc) (nc) dcy1 dcy2 (nc) m1 m2 (nc) cw/ccw 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 tq2 out_bm cw/ccw cl k reset osc n fb out_am pgnd a m o protect m1 dcy1 dcy2 m2 v dd vm a out_ap n fa out_bp pgndb vm b sgnd enable tq1
tb6560ahq/afg 2011-01-18 6 absolute maximum ratings (t a = 25c) characteristics symbol rating unit v dd 6 power supply voltage vm a/b 40 v tb6560ahq 3.5 output current (per phase) peak TB6560AFG i o (peak) 2.5 a m o drain current i (m o ) 1 ma protect drain current i (protect) 1 ma input voltage v in v dd v 5 (note 1) tb6560ahq 43 (note 2) 1.7 (note 3) power dissipation TB6560AFG p d 4.2 (note 4) w operating temperature t opr ? 30 to 85 c storage temperature t stg ? 55 to 150 c note 1: t a = 25c, without heatsink. note 2: t a = 25c, with infinite heatsink (hzip25). note 3: t a = 25c, with soldered leads. note 4: t a = 25c, when mounted on a board (4-layer board). operating range (t a = ? 30 to 85c) characteristics symbol test condition min typ. max unit v dd ? 4.5 5.0 5.5 v power supply voltage vm a/b vm a/b v dd 4.5 ? 34 v tb6560ahq ? ? ? 3 output current TB6560AFG i out ? ? ? 1.5 a input voltage v in ? 0 ? 5.5 v clock frequency f clk ? ? ? 15 khz osc frequency f osc ? ? ? 600 khz
tb6560ahq/afg 2011-01-18 7 electrical characteristics (t a = 25c, v dd = 5 v, vm = 24 v) characteristics symbol test condition min typ. max unit high v in (h) 2.0 ? v dd input voltage low v in (l) ? 0.2 ? 0.8 v input hysteresis voltage (note) v inhys m1, m2, cw/ccw, clk, reset , enable, dcy1, dcy2, tq1, tq2 ? 400 ? mv i in (h) m1, m2, cw/ccw, clk, reset , enable, dcy1, dcy2, tq1, tq2 v in = 5.0 v internal pull-down resistor 30 55 80 input current i in (l) v in = 0 v ? ? 1 a i dd1 outputs: open, reset : h, enable: h (2, 1-2 phase excitation) ? 3 5 i dd2 outputs: open, reset : h, enable: h (4w1 ? 2, 2w1-2 phase excitation) ? 3 5 i dd3 reset : l, enable: l ? 2 5 v dd supply current i dd4 reset : h, enable: l ? 2 5 ma i m1 reset : h/l, enable: l ? 0.5 1 vm supply current i m2 reset : h/l, enable: h ? 0.7 2 ma channel-to-channel voltage differential v o b/a, c osc = 330 f ? 5 ? 5 % v nfhh tq1 = h, tq2 = h 10 20 30 v nfhl tq1 = l, tq2 = h 45 50 55 v nflh tq1 = h, tq2 = l 70 75 80 v nf voltage change according to the torque settings v nfll tq1 = l, tq2 = l ? ? 100 % minimum clock pulse width t w (clk) c osc = 330 pf 30 ? ? s m o output residual voltage v ol m o i ol = 1 ma ? ? 0.5 v protect output rest voltage (note) v ol protect i ol = 1 ma ? ? 0.5 v tsd threshold (note) tsd ? ? 170 ? c tsd hysteresis (note) tsdhys ? ? 20 ? c oscillating frequency f osc c osc = 330 pf 60 130 200 khz note: not tested in production
tb6560ahq/afg 2011-01-18 8 electrical characteristics (t a = 25c, v dd = 5 v, vm = 24 v) characteristics symbol test condition min typ. max unit ron u1h ? 0.3 0.4 tb6560ahq ron l1h i out = 1.5 a ? 0.3 0.4 ron u1f ? 0.35 0.5 output on-resistance TB6560AFG ron l1f i out = 1.5 a ? 0.35 0.5 2w1-2- phase excitation 1-2- phase excitation = 0 ? 100 ? ? ? = 1/16 ? 100 ? 2w1-2- phase excitation ? = 2/16 93 98 100 ? ? = 3/16 91 96 100 2w1-2- phase excitation ? = 4/16 87 92 97 ? ? = 5/16 83 88 93 2w1-2- phase excitation ? = 6/16 78 83 88 ? ? = 7/16 72 77 82 2w1-2- phase excitation 1-2- phase excitation = 8/16 66 71 76 ? ? = 9/16 58 63 68 2w1-2- phase excitation ? = 10/16 51 56 61 ? ? = 11/16 42 47 52 2w1-2- phase excitation ? = 12/16 33 38 43 ? ? = 13/16 24 29 34 2w1-2- phase excitation ? = 14/16 15 20 25 4w1-2- phase excitation ? ? = 15/16 5 10 15 a-/b-phase chopping current (note 1) 2-phase excitation vector ? tq1 = l, tq2 = l ? 100 ? % reference voltage v nf tq1, tq2 = l (100 %) osc = 100 khz 450 500 550 mv t r ? 1 ? output transistor switching characteristics (note 2) t f r l = 10 , v nf = 0.5 v ? 1 ? t plh reset to output ? 1 ? t plh ? 3 ? delay time (note 2) t phl enable to output ? 2 ? s upper side i lh ? ? 1 output leakage current lower side i ll vm = 40 v ? ? 1 a note 1: relative to the peak current at = 0. note 2: not tested in production.
tb6560ahq/afg 2011-01-18 9 functional descriptions 1. excitation mode settings the excitation mode can be selected from the follo wing four modes using the m1 and m2 inputs. (the 2-phase excitation mode is selected by default since both m1 and m2 have internal pull-down resistors.) inputs m2 m1 mode (excitation) l l 2-phase l h 1-2-phase h l 4w1-2-phase h h 2w1-2-phase 2. function table (relationship between inputs and output modes) when the enable pin is low, outputs are off. when the reset pin is low, the outputs are put in the initial mode as shown in the table below. in this mode, the states of the clk and cw/ccw pins are don?t-cares. inputs clk cw/ccw reset enable output mode l h h cw h h h ccw x x l h initial mode x x x l z x: don?t care 3. initial mode when reset is asserted, phase currents in each excitati on mode are as follows. at this time, the m o pin goes low (open-drain connection). excitation mode a-phase current b-phase current 2-phase 100 % ? 100 % 1-2-phase 100 % 0 % 2w1-2-phase 100 % 0 % 4w1-2-phase 100 % 0 % 4. decay mode settings it takes approximately four osc cycles for discharging a current in pwm mode. the 25 % decay mode is created by inducing decay during the last cycle in fast decay mode; the 50 % decay mode is created by inducing decay during the last two cycles in fast decay mode; and the 100 % decay mode is created by inducing decay during all four cycles in fast decay mode. since the dcy1 and dcy2 pins have internal pull-down resistors, the normal mode is selected when dcy1 and dcy2 are undriven. dcy2 dcy1 current decay setting l l normal 0 % l h 25 % decay h l 50 % decay h h 100 % decay
tb6560ahq/afg 2011-01-18 10 5. torque settings (current value) the ratio of the current necessary for actual operations to the predefined current adjusted by an external resistor can be selected as follows. the weak excitati on mode should be selected to set a torque extremely low like when the motor is at a fixed position. since the tq2 and tq1 pins have pull-down resistors, the 100 % torque setting is selected when tq2 and tq1 are undriven. tq2 tq1 current ratio l l 100 % l h 75 % h l 50 % h h 20 % (weak excitation) 6. calculation of the predefined output current to perform a constant current drive, the reference current should be adjusted by an external resistor. charging stops when the n fa (n fb ) voltage reaches 0.5 v (when the torque setting is 100 %) so that a current does not exceed the predefined level. i out (a) = 0.5 (v) / r nf ( ) example: to set the peak current to 1 a, the value of an external re sistor should be 0.5 . 7. protect and m o output pins these are open-drain outputs. an ex ternal pull-up resistor should be added to these pins when in use. if the tsd circuit is activated, protect is driven low. when the ic ente rs the initial state, m o is driven low. pin state protect m o low thermal shutdown initial state high-z normal operation other than the initial state rest voltage of output terminal mo and output terminal protect reach 0.5 v (max) when i o is 1 ma. 8. adjusting the external capacitor value (c osc ) and minimum clock pulse width (t w(clk) ) a triangular-wave is generated intern ally by cr oscillation. the capacito r is externally connected to the osc pin. the recommended capacitor value is between 100 pf and 1000 pf. approximate equation: f osc = 1/ { c osc 1.5 (10/ c osc + 1)/66 } 1000 khz (since this is an approximation fo rmula, the calculation result may not be exactly equal to the actual value.) the approximate values are shown below. the minimum clock pulse width (t w(clk) ) corresponds to the external capacitor (c osc ) as follows: capacitor oscillating frequency mi nimum clock pulse width t w(clk) (note 1) 1000 pf 44 khz 90 s (note 2) 330 pf 130 khz 30 s 100 pf 400 khz 10 s (note 2) note 1: when the frequency of an input clock signal is high, the c osc value should be small so that the duty cycle of an input clock pulse does not become extremely high (should be around 50 % or lower). note 2: not tested in production. open-drain connection
tb6560ahq/afg 2011-01-18 11 relationship between the enable and and output signals example 1: enable input in 1-2-phase excitation mode (m1: h, m2: l) setting the enable signal low disables only the output signals, while internal circuitry other than the output block continues to operate in accordance with the clk input. therefore, wh en the enable signal goes high again, the output current generation is rest arted as if phases proceeded with the clk signal. example 2: reset input in 1-2-phase excitation mode (m1: h, m2: l) setting the reset signal low causes the outputs to be put in the initial state and the m o output to be driven low (initial state: a-channel ou tput current is at its peak (100 %)). when the reset signal goes high again, the ou tput current generation is rest arted at the next rising edge of clk with the state following the initial state. clk enable reset m o voltage 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 8 t 9 t 10 t 11 t 12 off 71 ? 71 i a (current from out_ap to out_am) cw clk enable reset m o voltage 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 2 t 3 71 ? 71 t 6 i a (current from out_ap to out_am) cw reset
tb6560ahq/afg 2011-01-18 12 2-phase excitation (m1: l, m2: l, cw mode) 1-2-phase excitation (m1: h, m2: l, cw mode) clk m o 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 4 t 5 t 6 i a cw 100 (%) 0 ? 100 i b clk m o 100 (%) 0 ? 100 t 0 t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 6 71 ? 71 i a 100 (%) 0 ? 100 71 ? 71 i b cw
tb6560ahq/afg 2011-01-18 13 2w1-2-phase excitation (m1: h, m2: h, cw mode) i b i a clk t 0 t 1 t 2 t 3 t 7 t 8 t 4 t 5 t 12 t 13 t 6 cw m o 100 (%) 98 92 83 71 56 38 20 0 ? 20 ? 38 ? 56 ? 71 ? 83 ? 92 ? 98 ? 100 100 (%) 98 92 83 71 56 38 20 0 ? 20 ? 38 ? 56 ? 71 ? 83 ? 92 ? 98 ? 100 t 9 t 10 t 11 t 14 t 17 t 18 t 15 t 16 t 19 t 20 t 21 t 22 t 23 t 27 t 28 t 24 t 25 t 26 t 29 t 30 t 31 t 32
tb6560ahq/afg 2011-01-18 14 4w1-2-phase excitation (m1: l, m2: h, cw mode) ? 100 step ? 98 0 ? 96 ? 88 ? 92 ? 77 ? 71 ? 56 ? 63 ? 47 ? 38 ? 29 ? 20 ? 10 ? 83 10 20 29 38 47 56 63 71 77 83 88 92 96 98 100 [%] a-phase b-phase
tb6560ahq/afg 2011-01-18 15 it is recommended that the state of the m1 and m2 pins be changed after setting the reset signal low during the initial state (m o = low). even when the m o signal is low, changing the m1 and m2 signals without setting the reset signal low may cause a discontinuity in the current waveform. ck m2 100 (%) 0 1-2-phase excitation 91 i a 71.4 40 ? 40 ? 71.4 ? 91 ? 100 m1 reset other excitation o m
tb6560ahq/afg 2011-01-18 16 9. current waveforms and mixed decay mode settings the current decay rate of the decay mode operation ca n be determined by the dcy1 and dcy2 inputs for constant-current control. the ?nf? refers to the point at which the output cu rrent reaches its predefined current level, and the ?rnf? refers to the monitoring timing of the predefined current. the smaller the mdt value, the sma ller the current ripple amplitude. however, the current decay rate decreases. nf normal mode rnf predefined current level osc pin internal waveform f chop nf 25 % decay mode rnf mdt predefined current level nf 50 % decay mode rnf mdt predefined current level nf 100 % decay mode rnf predefined current level charge mode nf: predefined current level slow mode current monitoring (when predefined current level > output current) charge mode charge mode nf: predefined current level slow mode mixed decay timing fast mode current monitoring (when predefined current level > output current) charge mode charge mode nf: predefined current level slow mode mixed decay timing fast mode current monitoring (when predefined current level > output current) charge mode charge mode nf: predefined current level fast mode current monitoring (when predefined current level > output current) charge mode
tb6560ahq/afg 2011-01-18 17 10. current control modes (effects of decay modes) ? increasing the current (sine wave) ? decreasing the current with a high decay rate (the cu rrent decay rate in mixed decay mode is the ratio between the time in fast-decay mode (discharge ti me after mdt) and the remainder of the period.) ? decreasing the current with a low decay rate (the current decay rate in mixed decay mode is the ratio between the time in fast-decay mode (discharge ti me after mdt) and the remainder of the period.) during mixed decay and fast decay modes, if the predefined current level is less than the output current at the rnf (current moni toring point), the charge mode in the next chopping cycle will disappear (though the current control mode is briefly switched to charge mode in actual operations for current sensing) and the current is controlled in sl ow and fast decay modes (mode switching from slow decay mode to fast decay mode at the mdt point). note: the above figures are rough illustration of the output current. in actual current waveforms, transient response curves can be observed. slow slow slow slow fast fast charge charge fast charge fast charge predefined current level predefined current level slow slow fast charge fast charge slow fast slow fast charge since the current decays quickly, it can be decreased to the predefined value in a short time. predefined current level predefined current level slow fast charge slow fast charge fast slow fast slow since the current decays slowly, decreasing the current to the predefined value takes a long time (or the current cannot be properly decreased to the predefined value). predefined current level predefined current level
tb6560ahq/afg 2011-01-18 18 11. current waveforms in mixed decay mode ? when the nf points come after mixed decay timing points ? when the output current value > predefined current level in mixed decay mode * : even if the output current rises above the predefined current at the rnf point, the current control mode is briefly switched to charge mode for current sensing. nf nf 25 % mixed decay mode osc pin internal waveform i out f chop f chop predefined current level predefined current level rnf mdt (mixed decay timing) points nf nf 25 % mixed decay mode i out f chop f chop predefined current level predefined current level rnf mdt (mixed decay timing) points clk signal input switches to fast mode after charge mode rnf nf nf 25 % mixed decay mode i out f chop f chop predefined current level clk signal input f chop mdt (mixed decay timing) points predefined current level rnf rnf
tb6560ahq/afg 2011-01-18 19 12. current waveform in fast decay mode after the output current to the load reaches the curren t value specified by rnf, to rque or other means, the output current to the load will be fed back to the power supply fully in fast decay mode. f chop clk signal input fast decay mode (100 % decay mode) predefined current level i out nf since the predefined current level > output current, current control mode is switched from charge mode nf fast decay mode even in the next chopping cycle. rnf rnf rnf predefined current level switches to charge mode briefly
tb6560ahq/afg 2011-01-18 20 13. clk and internal osc signals and output current waveform (when the clk signal is asserted during slow decay mode) when the clk signal is asserted, th e chopping counter (osc counter) is forced to reset at the next rising edge of the osc signal. as a result, the response to input data is faster co mpared to methods in which the counter is not reset. the delay time that is theoretically determ ined by the logic circuit is one osc cycle = 10 s at a 100-khz chopping rate. after the osc counter is reset by the clk signal input, the current control mode is invariably switched to charge mode briefly for current sensing. note: even in fast decay mode, the current control mo de is invariably switched to charge mode briefly for current sensing. 25 % mixed decay mode clk signal input predefined current level i out rnf predefined current level f chop osc pin internal waveform switches to charge mode briefly the osc counter is reset here. nf rnf mdt nf mdt f chop f chop
tb6560ahq/afg 2011-01-18 21 14. clk and internal osc signals and output current waveform (when the clk signal is asserted during charge mode) mdt 25 % mixed decay mode clk signal input predefined current level i out rnf predefined current level f chop osc pin internal waveform switches to charge mode briefly the osc counter is reset here. nf rnf mdt f chop f chop
tb6560ahq/afg 2011-01-18 22 15. clk and internal osc signals and output current waveform (when the clk signal is asserted during fast decay mode) nf clk signal input i out rnf predefined current level f chop osc pin internal waveform switches to charge mode briefly the osc counter is reset here. f chop f chop mdt nf rnf mdt predefined current level 25 % mixed decay mode
tb6560ahq/afg 2011-01-18 23 16. internal osc signal and output current waveform when predefined current is changed from positive to negative (when the clk signal is input using 2-phase excitation) 25% mixed decay mode clk signal input f chop the osc counter is reset here. f chop f chop predefined current level i out rnf predefined current level nf rnf 0 mdt nf
tb6560ahq/afg 2011-01-18 24 current discharge path when enab le is set as low during operation when all the output transist ors are forced off during slow decay mode , the coil energy is discharged in the following modes: note: parasitic diodes are located on dotted lines. howeve r, they are not normally used in normal mixed decay mode. as shown in the figure above, output transistors have parasitic diodes. normally, when the energy of the coil is discharged, each transist or is turned on allowing the current to flow in the reverse direction to that in normal operation; as a re sult, the parasitic diodes are not used. however, when all the output transistors are forced off, the coil energy is discha rged via the parasitic diodes. u1 l1 u2 l2 pgnd off off u1 l1 u2 l2 off on note load pgnd u1 l1 u2 l2 off off note load pgnd note r nf vm on on load charge mode slow mode forced off mode on r nf vm r nf vm off off enable is set as low off
tb6560ahq/afg 2011-01-18 25 output transistor operating modes output transistor operating modes clk u1 u2 l1 l2 charge on off off on slow decay off off on on fast decay off on on off note: this table shows an example of when the current flow s as indicated by the arrows in the above figures. if the current flows in the opposite directi on, refer to the following table: clk u1 u2 l1 l2 charge off on on off slow decay off off on on fast decay on off off on upon transitions of above-mentioned modes, a dead time of about 300 ns is inserted between each mode respectively. u1 l1 u2 l2 pgnd off off u1 l1 u2 l2 off on note load pgnd u1 l1 u2 l2 note load pgnd note r nf vm on on load charge mode slow mode fast mode on r nf vm r nf vm off off off on on
tb6560ahq/afg 2011-01-18 26 test points for ac specifications figure 1 timing waveforms and symbols osc-charge delay: the osc waveform is converted into the internal osc waveform by checking the level of a chopping wave. the internal osc signal is designed to be logic high when the osc voltage is at 2 v or above, and to be logic low when the osc voltage is at 0.5 v or below. howeve r, there is a response dela y and that there occurs a peak-to-peak voltage variation. figure 2 timing waveforms (osc signal) clk t clk t clk t plh t phl vm gnd t r t f 10% 50% 90% 90% 50% 10% osc waveform osc pin internal waveform 2 v 0.5 v
tb6560ahq/afg 2011-01-18 27 power dissipation tb6560ahq TB6560AFG power dissipation p d (w) with soldered leads. when mounted on a board (4-layer board) p d - ta ambient temperature ta ( )
tb6560ahq/afg 2011-01-18 28 1. power-on sequence with control input signals turn on v dd . then, when the v dd voltage has stabilized, turn on vm a/b . hold the control input pins low while turning on v dd and vm a/b . (all the control input pins ar e internally pulled down.) after v dd and vm a/b completely stabilizes at the rated voltages, the reset and enable pins can be set high. if this sequence is not properly followed, the ic may not operate correctly, or the ic and the peripheral parts may be damaged. when reset is released high, the clk signal is applied and excitation is started. only after enable is also set high, output s are enabled. when only reset is set high, outputs are disabled and only the internal counter advances. likewise, when only enabl e is set high, the excitation will not be performed even if the clk signal is applied and the outputs will remain in the initial state. an example of a control inpu t sequence is shown below. a power-off sequence should be the reverse of this sequence. 2. power dissipation the power dissipation of the ic can be calculated by the following equation: p = v dd i dd + i out i out ron 2 phases the higher the ambient temperature, the smaller the power dissipation. examine the pd-t a characteristic curve to determine if there is a sufficient margin in the thermal design. 3. treatment of heat-radiating fin the heat-radiating fin pins of the tb6560ahq/afg (backside) are electrically connected to the backside of the die. thus, if a current flows to the fin, the ic ma y malfunction. if there is an y possibility of a voltage being generated between grounds and the fin, the fin pins should either be connected to ground or insulated. 4. thermal shutdown (tsd) when the die temperature reaches 170c (typ.), the thermal shutdown circuit is tripped, switching the outputs to off. there is a variation of about 20c in the temperature at which the thermal shutdown circuit is tripped. output z z output current setting internal current setting out enable h l h l reset h l clk internal current setting: disabled; output off internal current setting: enabled
tb6560ahq/afg 2011-01-18 29 application circuit example note: capacitors for the power supply lines should be connected as close to the ic as possible. usage considerations ? a large current might abruptly flow through the ic in ca se of a short-circuit across its outputs, a short-circuit to power supply or a short-circuit to ground, leading to a damage of the ic. also, the ic or peripheral parts may be permanently damaged or emit smoke or fire resu lting in injury especially if a power supply pin (v dd , vm a , vm b ) or an output pin (out_ap, out_am, out_bp, out_bm) is short-circuited to adjacent or any other pins. these possibilities should be fully considered in the design of the output, v dd , vm, and ground lines. ? a fuse should be connected to the power supply li ne. the rated maximum curr ent of the tb6560ahq is 3.5 a/phase and that of the tb 6560afg is 2.5 a/phase. consi dering those maximum ratings, an appropriate fuse must be selected depending on oper ating conditions of a motor to be used. toshiba recommends that a fast-blow fuse be used. ? the power-on sequence described on page 28 must be properly followed. ? if a voltage outside the operating range specified on page 6 (4.5 v dd 5.5, 4.5 vm a/b 34, v dd vm a/b ) is applied, the ic may not operate properly or the ic and peripheral parts may be permanently damaged. ensure that the voltage ran ge does not exceed the upper and lower limits of the specified range. nfcompa m mcu or external input clk reset enable m1 m2 cw/ccw dcy1 dcy2 tq1 tq2 protect m o r1 r2 osc 100 pf 400 khz sgnd pgnd fuse 10 f 5 v 1 f v dd vm a vm b 1 f 47 f 24 v logic current control h-sw a h-sw b out_ap out_am out_bp out_bm r nfa r nfb n fa n fb nfcompb 0.5 : i out (max) = 1.0 a pwm control circuit pwm control circuit
tb6560ahq/afg 2011-01-18 30 package dimensions weight: 9.86 g (typ.)
tb6560ahq/afg 2011-01-18 31 package dimensions weight: 0.26 g (typ.) note: the size of a backside heatsink is 5.5 mm 5.5 mm.
tb6560ahq/afg 2011-01-18 32 notes on contents 1. block diagrams some of the functional blocks, circu its, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are provided for re ference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by prov iding these examples of application circuits. 5. test circuits components in the test circuits are used only to obtain and confirm the devi ce characteristics. these components and circuits are not guaranteed to prev ent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics (1) the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or ic failure. the ic will fully break down when used under conditions that exceed its absolute maximum rating s, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large curren t to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. (3) if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negati ve current resulting from the back electromotive force at power off. ic breakdown may cause inju ry, smoke or ignition. use a stable power supply with ics with built-in protec tion functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. (4) do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative term inals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time.
tb6560ahq/afg 2011-01-18 33 points to remember on handling of ics (1) thermal shutdown circuit thermal shutdown circuits do not necessarily prot ect ics under all circumst ances. if the thermal shutdown circuits operate agains t the over temperature, clear the heat generation status immediately. depending on the method of use and usage condit ions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not oper ate properly or ic brea kdown before operation. (2) heat radiation design in using an ic with large current flow such as power amp, regulator or driver, please design the device so that heat is appropriately radiated, no t to exceed the specified junction temperature (t j ) at any time and condition. these ics generate heat ev en during normal use. an inadequate ic heat radiation design can lead to decrease in ic life, dete rioration of ic characterist ics or ic breakdown. in addition, please design the device taking into co nsiderate the effect of ic heat radiation with peripheral components. (3) back-emf when a motor rotates in the reverse direction, stop s or slows down abruptly, a current flow back to the motor?s power supply due to the effect of back- emf. if the current sink capability of the power supply is small, the device?s motor power supply an d output pins might be exposed to conditions beyond maximum ratings. to avoid this problem, ta ke the effect of back-emf into consideration in system design. (4) short-circuits the ic may be permanently damaged in case of a short-circuit across its outputs, a short-circuit to power supply or a short-circuit to ground. these possibilities should be fully co nsidered in the design of the output, v dd , vm and ground lines. (5) short-circuits between adjace nt pins in the tb6560ahq in the tb6560ahq, the term ?adjacent pin? includes a pin diagonally closest to a given pin. for example, pin 3 has four adjacent pins: 1, 2, 4 and 5. depending on the specified voltag e and current, a large current might abruptly flow through the tb6560ahq in case of a short-circuit between any adjacent pins that are listed below. if the large current persists, it may lead to a smoke emission. 1) pins 7 and 8 2) pins 7 and 9 3) pins 8 and 9 4) pins 9 and 10 5) pins 9 and 11 6) pins 10 and 12 7) pins 11 and 12 8) pins 11 and 13 9) pins 12 and 13 10) pins 12 and 14 11) pins 13 and 14 12) pins 13 and 15 13) pins 14 and 16 14) pins 15 and 16 15) pins 16 and 17 16) pins 16 and 18 17) pins 17 and 18 18) pins 18 and 19 19) pins 18 and 20 therefore, to avoid a continuous overcurrent due to the above-des cribed short-circuit and allow the tb6560ahq/afg to be fail-safe, an appropriate fuse should be added at the right place, or overcurrent shutdown circuitry should be added to the power supply. the rated current of a fuse may vary depending on actual applications and its characteristics. thus, an appropriate fuse must be selected experimentally.
tb6560ahq/afg 2011-01-18 34 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software an d systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduc tion is permissible only if reproducti on is without alteration/omission. ? though toshiba works continually to improve product?s quality a nd reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for prov iding adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situat ions in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, cu stomers must also refer to and comply with (a) the latest ve rsions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and condi tions set forth in the ?toshiba semiconductor reliability handbook? and (b) the instructions for the application with which the product will be us ed with or for. customers are solely responsible for all aspe cts of their own product design or applications , including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in c harts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operatin g parameters for such designs and applications. toshiba assumes no liability for customers? product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document . product is neither intended nor warranted for use in equipment or sy stems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic s ignaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to el ectric power, and equipment used in finance-related fields. do not use product for unintended use unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this documen t, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related soft ware or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical , or biological weapons or missi le technology products (mass destruction w eapons). product and related software and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. expor t administration regulations. ex port and re-export of product or related software or technology are strictly prohibited exc ept in compliance with all applicable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations.

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